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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
Advance Information LCD Segment / Common Driver with Controller
CMOS
SSD1820A/21 is a single-chip CMOS LCD driver with controller for a liquid crystal dot-matrix graphic display system. SSD1820A consists of 194 high voltage driving output pins for driving 128 Segments, 64 Commons and 2 icon driving Commons, while SSD1821 consists of 210 high voltage driving output pins for driving 128 Segments, 80 Commons and 2 icon driving Commons.
SSD1820A SSD1821
TAB
SSD1820A/21 displays data directly from its internal 128x65/128X81 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a hardware selectable 6800-/8080-series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface. SSD1820A/21 embeds a DC-DC Converter, a LCD Voltage Regulator, an OnChip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1820A/21 is suitable for any portable battery-driven applications requiring a long operation period and a compact size.
Gold Bump Die
ORDERING INFORMATION SSD1820AZ SSD1821Z SSD1820ATR1 SSD1821TR1 Gold Bump Die Gold Bump Die TAB TAB
* * * * * * * * * * * * * * * * * * * *
128 x 64/80 Graphic Display with a Icon Line Programmable Multiplex ratio [16Mux - 65Mux/81Mux] (Partial Display) Single Supply Operation, 1.8 V - 3.3V Low Current Sleep Mode(<1.0uA) On-Chip Voltage Generator / External Power Supply Software selectable 2X / 3X / 4X / 5X / 6X On-Chip DC-DC Converter On-Chip Oscillator Software Selectable On-Chip Bias Dividers Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio Maximum +15.0V LCD Driving Output Voltage Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface On-Chip 128 x 65/81 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control 64 Levels Internal Contrast Control External Contrast Control Maximum 17MHz SPI or 15MHz PPI operation Selectable LCD Driving Voltage Temperature Coefficients (2 settings) Available in Gold Bump Die and Standard TAB (Tape Automated Bonding) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copyright (c) 2002/2003 Solomon Systech Limited.
REV 1.4 01/03
Block Diagram
ICONS
COM0 to COM63/79 SEG0~SEG127
HV Buffer Cell Level Shifter
Level Selector
193 Bit Latch (SSD1820A) 209 Bit Latch (SSD 1821)
VL6 VL5 VL4 VL3 VL2 V SS VR V CC C 1P C 2P C 3P C 4P C 5P C 1N C 2N REF INTRS VC I VE X T
Display Timing Generator
LCD Driving Voltage Generator 2X / 3X / 4X / 5X /6X DC/DC Converter, Voltage Regulator, Bias Divider, Contrast Control, Temperature Compensation
CL
Oscillator GDDRAM 128 X 65 Bits (SSD1820A) 128 x 81 Bits (SSD1821)
Command Decoder
V SS VDD Command Interface Parallel / Serial Interface
RES PS0
PS1
CS
D/C
R/W E (WR) (RD)
D7 D6 D 5 D 4 D 3 D 2 D 1 D0 (SDA)(SCK)
SSD1820A/21 REV 1.4 01/03 2
SOLOMON
N/C PS1 /CS /RES D/C R/W (/WR) E (/RD) D0 D1 D2 D3 D4 D5 D6 D7 VDD VSS VCC C3P C1N C1P C2P C2N NC VL2 VL3 VL4 VL5 VL6 VR CL N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
233 232 231 230 229 228
199 198 197 196 195
70 69 68 67 66
38 37 36 35 34 33
N/C N/C N/C ICONS COM63 COM62 : : : : : : COM33 COM32 N/C SEG127 SEG126 : : : : : : SEG1 SEG0 ICONS COM0 COM1 : : : : : : COM29 COM30 COM31 N/C N/C N/C
Note : PS0, REF, INTRS and VCI are connected to VDD Set condition: Parallel interface, internal reference voltage, internal voltage regulator and Booster reference voltage is VDD SSD1820ATRPin Assignment SSD1820AT Pin Assignment (Copper View)
SOLOMON
REV 1.4 01/03
SSD1820A/21 3
N/C CL VR VL6 VL5 VL4 VL3 VL2 INTRS C4P C2N C2P C1P C1N C3P C5P VCC VSS VCI VDD D7(SDA) D6(SCK) D5 D4 D3 D2 D1 D0 E (/RD) R/W (/WR) D/C /RES /CS PS1 PS0 N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
247 246 245 244 243
N/C COM39 COM38 COM37 COM36 : : : : : : COM1 COM0 ICONS SEG0 SEG1 : : : : : : SEG125 SEG126 SEG127 COM40 COM41 : : : : : : COM75 COM76 COM77 COM78 COM79 ICONS
208 207 206 205 204
80 79 78 77 76
42 41 40 39 38 37
Note : REF connected to VDD
SSD1821T Pin Assignment (Copper View)
SSD1820A/21 REV 1.4 01/03 4
SOLOMON
N/C COM 6 COM 7 COM 8 COM 9 : : : : : : : : : : : COM 28 COM 29 COM 30 COM 31 N/C COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM32 COM33 COM34 COM35 COM36 COM37 COM38
144
115
:
: :
285
1
N/C N/C : N/C CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS INTRS VDD VEXT REF VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P N/C N/C N/C VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VCI VDD VDD VDD D7 (SDA) D7 (SDA) D6 (SCK) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E(/RD) E(/RD) R/W(/WR) R/W(/WR) VSS D/C D/C D/C /RES VDD /CS /CS VSS PS1 VDD VSS PS0 VDD N/C N/C : : N/C N/C
Note: 1. Diagram showing the face of the die. 2. Coordinates are reference to center of the chip. 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bump.
Y
x (0,0 )
Pin#1 Die Size: 10.8mm x 1.96mm Die Thickness: 534um +/- 25um Bump Height: 18um +/- 3um
SSD1820AZ Die Pin Assignment DRAWING NOT TO SCALE SOLOMON
REV 1.4 01/03
N /C COM39 COM40 COM41 COM42 : : : : : : : : : : : COM61 COM62 COM63 ICONS N /C
SSD1820A/21 5
N/C COM 6 COM 7 COM 8 COM 9 : : : : : : : : : : : COM 28 COM 29 COM 30 COM 31 N/C COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM40 COM41 COM42 COM43 COM44 COM45 COM46
144
115
:
285 1
N /C COM47 COM48 COM49 COM50 : : : : : : : : : : : COM69 COM70 COM71 COM72 N /C
:
COM32 : COM39 CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS INTRS VDD VEXT REF VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P C5P C5P C5P VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VCI VDD VDD VDD D7 (SDA) D7 (SDA) D6 (SCK) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E(/RD) E(/RD) R/W(/WR) R/W(/WR) VSS D/C D/C D/C /RES VDD /CS /CS VSS PS1 VDD VSS PS0 VDD N/C N/C N/C N/C ICONS COM79 : COM73
Note: 1. Diagram showing the face of the die. 2. Coordinates are reference to center of the chip. 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bump.
Y
x (0,0 )
Pin#1
SSD1821Z Die Pin Assignment DRAWING NOT TO SCALE SSD1820A/21 REV 1.4 01/03 6
Die Size: 10.8mm x 1.96mm Die Thickness: 534um +/- 25um Bump Height: 18um +/- 3um
SOLOMON
SSD1820AZ & SSD1821Z Alignment Key Position
Y (0,0) X
Center (-3926.1, 120)
Notes: 1. Diagram showing the gold bump view of the die. 2. Coordinates are reference to center of the chip 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bmup. 5. `X' represents the center point. 6. Drawing not to scale
Pin#1
22.5um 22.5um 22.5um
22.5um
99.9um
99.9um
67.5um
67.5um
x
x
x
Center (3991.5, 120)
Center (4409.4, -147.9)
50.1um 78.75um
10.98um
70.875um
58.35um
18.9um
51.9um
78.75um
99.9um
x
x
10.65um
49.8um
Center (-4095, -64.65) Center (4263, -64.65)
52.2um
100.2um
Center (4515.6, -148.05)
SOLOMON
REV 1.4 01/03
SSD1820A/21 7
SSD1820A/21Z Die Pad Coordinates
Pad# SSD1820A SSD1821 1 N/C COM73 2 N/C COM74 3 N/C COM75 4 N/C COM76 5 N/C COM77 6 N/C COM78 7 N/C COM79 8 N/C ICONS 9 NC NC 10 NC NC 11 NC NC 12 NC NC 13 VDD VDD 14 PS0 PS0 15 VSS VSS 16 VDD VDD 17 PS1 PS1 18 VSS VSS 19 /CS /CS 20 /CS /CS 21 VDD VDD 22 /RES /RES 23 D/C D/C 24 D/C D/C 25 D/C D/C 26 VSS VSS 27 R/W R/W 28 R/W R/W 29 E E 30 E E 31 VDD VDD 32 D0 D0 33 D1 D1 34 D2 D2 35 D3 D3 36 D4 D4 37 D5 D5 38 D6 D6 39 D6 D6 40 D7 D7 41 D7 D7 42 VDD VDD 43 VDD VDD 44 VDD VDD 45 VCI VCI 46 VCI VCI 47 VCI VCI 48 VCI VCI 49 VCI VCI 50 VSS VSS 51 VSS VSS 52 VSS VSS 53 VSS VSS 54 VSS VSS 55 VSS VSS 56 VCC VCC 57 VCC VCC 58 VCC VCC 59 VCC VCC 60 NC C5P 61 NC C5P 62 NC C5P 63 C3P C3P 64 C3P C3P 65 C3P C3P 66 C1N C1N 67 C1N C1N 68 C1N C1N 69 C1N C1N 70 C1P C1P 71 C1P C1P x-pos -4568.40 -4503.60 -4438.80 -4374.00 -4309.20 -4244.40 -4179.60 -4114.80 -3964.80 -3887.40 -3810.00 -3732.60 -3634.28 -3558.08 -3481.88 -3405.68 -3329.48 -3253.28 -3177.08 -3100.88 -3024.68 -2948.48 -2872.28 -2796.08 -2719.88 -2643.68 -2567.48 -2491.28 -2415.08 -2338.88 -2262.68 -2186.48 -2110.28 -2034.08 -1957.88 -1881.68 -1805.48 -1729.28 -1653.08 -1576.88 -1500.68 -1424.48 -1348.28 -1272.08 -1149.90 -1073.70 -997.50 -921.30 -845.10 -768.90 -692.70 -616.50 -540.30 -464.10 -387.90 -311.70 -230.40 -149.10 -67.80 13.50 94.80 176.10 257.40 338.70 420.00 536.70 612.90 689.10 765.30 882.00 963.30 y-pos -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -807.45 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 Pad# SSD1820A SSD1821 116 N/C N/C 117 COM31 COM31 118 COM30 COM30 119 COM29 COM29 120 COM28 COM28 121 COM27 COM27 122 COM26 COM26 123 COM25 COM25 124 COM24 COM24 125 COM23 COM23 126 COM22 COM22 127 COM21 COM21 128 COM20 COM20 129 COM19 COM19 130 COM18 COM18 131 COM17 COM17 132 COM16 COM16 133 COM15 COM15 134 COM14 COM14 135 COM13 COM13 136 COM12 COM12 137 COM11 COM11 138 COM10 COM10 139 COM9 COM9 140 COM8 COM8 141 COM7 COM7 142 COM6 COM6 143 N/C N/C x-pos 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 5191.50 y-pos -874.80 -810.00 -745.20 -680.40 -615.60 -550.80 -486.00 -421.20 -356.40 -291.60 -226.80 -162.00 -97.20 -32.40 32.40 97.20 162.00 226.80 291.60 356.40 421.20 486.00 550.80 615.60 680.40 745.20 810.00 874.80 Pad# SSD1820A SSD1821 144 COM5 COM5 145 COM4 COM4 146 COM3 COM3 147 COM2 COM2 148 COM1 COM1 149 COM0 COM0 150 ICONS ICONS 151 SEG0 SEG0 152 SEG1 SEG1 153 SEG2 SEG2 154 SEG3 SEG3 155 SEG4 SEG4 156 SEG5 SEG5 157 SEG6 SEG6 158 SEG7 SEG7 159 SEG8 SEG8 160 SEG9 SEG9 161 SEG10 SEG10 162 SEG11 SEG11 163 SEG12 SEG12 164 SEG13 SEG13 165 SEG14 SEG14 166 SEG15 SEG15 167 SEG16 SEG16 168 SEG17 SEG17 169 SEG18 SEG18 170 SEG19 SEG19 171 SEG20 SEG20 172 SEG21 SEG21 173 SEG22 SEG22 174 SEG23 SEG23 175 SEG24 SEG24 176 SEG25 SEG25 177 SEG26 SEG26 178 SEG27 SEG27 179 SEG28 SEG28 180 SEG29 SEG29 181 SEG30 SEG30 182 SEG31 SEG31 183 SEG32 SEG32 184 SEG33 SEG33 185 SEG34 SEG34 186 SEG35 SEG35 187 SEG36 SEG36 188 SEG37 SEG37 189 SEG38 SEG38 190 SEG39 SEG39 191 SEG40 SEG40 192 SEG41 SEG41 193 SEG42 SEG42 194 SEG43 SEG43 195 SEG44 SEG44 196 SEG45 SEG45 197 SEG46 SEG46 198 SEG47 SEG47 199 SEG48 SEG48 200 SEG49 SEG49 201 SEG50 SEG50 202 SEG51 SEG51 203 SEG52 SEG52 204 SEG53 SEG53 205 SEG54 SEG54 206 SEG55 SEG55 207 SEG56 SEG56 208 SEG57 SEG57 209 SEG58 SEG58 210 SEG59 SEG59 211 SEG60 SEG60 212 SEG61 SEG61 213 SEG62 SEG62 214 SEG63 SEG63 x-pos 4568.40 4503.60 4438.80 4374.00 4309.20 4244.40 4179.60 4114.80 4050.00 3985.20 3920.40 3855.60 3790.80 3726.00 3661.20 3596.40 3531.60 3466.80 3402.00 3337.20 3272.40 3207.60 3142.80 3078.00 3013.20 2948.40 2883.60 2818.80 2754.00 2689.20 2624.40 2559.60 2494.80 2430.00 2365.20 2300.40 2235.60 2170.80 2106.00 2041.20 1976.40 1911.60 1846.80 1782.00 1717.20 1652.40 1587.60 1522.80 1458.00 1393.20 1328.40 1263.60 1198.80 1134.00 1069.20 1004.40 939.60 874.80 810.00 745.20 680.40 615.60 550.80 486.00 421.20 356.40 291.60 226.80 162.00 97.20 32.40 y-pos 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 Pad# SSD1820A SSD1821 286 N/C N/C 287 COM39 COM47 288 COM40 COM48 289 COM41 COM49 290 COM42 COM50 291 COM43 COM51 292 COM44 COM52 293 COM45 COM53 294 COM46 COM54 295 COM47 COM55 296 COM48 COM56 297 COM49 COM57 298 COM50 COM58 299 COM51 COM59 300 COM52 COM60 301 COM53 COM61 302 COM54 COM62 303 COM55 COM63 304 COM56 COM64 305 COM57 COM65 306 COM58 COM66 307 COM59 COM67 308 COM60 COM68 309 COM61 COM69 310 COM62 COM70 311 COM63 COM71 312 ICONS COM72 313 N/C N/C x-pos -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 -5191.50 y-pos 874.80 810.00 745.20 680.40 615.60 550.80 486.00 421.20 356.40 291.60 226.80 162.00 97.20 32.40 -32.40 -97.20 -162.00 -226.80 -291.60 -356.40 -421.20 -486.00 -550.80 -615.60 -680.40 -745.20 -810.00 -874.80
SSD1820A/21 REV 1.4 01/03 8
SOLOMON
SSD1820A/21Z Die Pad Coordinates
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 10 1 11 1 12 1 13 1 14 1 15 1 C1P C2P C2P C2P C2N C2N C2N C2N C4P C4P C4P VSS REF VEXT VDD INTRS VSS VL2 VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 VR VR VSS CL N/C N/C N/C N/C N/C N/C N/C N/C C1P C2P C2P C2P C2N C2N C2N C2N C4P C4P C4P VSS REF VEXT VDD INTRS VSS VL2 VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 VR VR VSS CL COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 1044.60 1125.90 1207.20 1288.50 1405.20 1481.40 1557.60 1633.80 1750.50 1831.80 1913.10 1989.30 2065.50 2182.20 2258.40 2334.60 2410.80 2487.00 2568.30 2649.60 2730.90 2812.20 2893.50 2974.80 3056.10 3137.40 3218.70 3300.00 3381.30 3462.60 3543.90 3625.20 3741.90 3818.10 3894.30 3970.50 4114.80 4179.60 4244.40 4309.20 4374.00 4438.80 4503.60 4568.40 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -780.75 -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 -773.40 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM32 COM33 COM34 COM35 COM36 COM37 COM38 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM40 COM41 COM42 COM43 COM44 COM45 COM46 -32.40 -97.20 -162.00 -226.80 -291.60 -356.40 -421.20 -486.00 -550.80 -615.60 -680.40 -745.20 -810.00 -874.80 -939.60 -1004.40 -1069.20 -1134.00 -1198.80 -1263.60 -1328.40 -1393.20 -1458.00 -1522.80 -1587.60 -1652.40 -1717.20 -1782.00 -1846.80 -1911.60 -1976.40 -2041.20 -2106.00 -2170.80 -2235.60 -2300.40 -2365.20 -2430.00 -2494.80 -2559.60 -2624.40 -2689.20 -2754.00 -2818.80 -2883.60 -2948.40 -3013.20 -3078.00 -3142.80 -3207.60 -3272.40 -3337.20 -3402.00 -3466.80 -3531.60 -3596.40 -3661.20 -3726.00 -3790.80 -3855.60 -3920.40 -3985.20 -4050.00 -4114.80 -4179.60 -4244.40 -4309.20 -4374.00 -4438.80 -4503.60 -4568.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40 773.40
y x
Bump size : Pad 1~8, 108~115, 144~285 : Pad 9~107 : Pad 116~143, 286~313 : Tolerance : +/- 3um
45x75um 52.2x60um 75x45um
SSD1820A /21
Pad 1, 2, 3, ..... -> 115
SOLOMON
REV 1.4 01/03
SSD1820A/21 9
PIN DESCRIPTIONS
RES This pin is reset signal input. When the pin is low, initialization of the chip is executed. PS0 This pin use together with PS1 to determine the interface protocol between the driver and MCU. Refer to PS1 pin descriptions for more details. PS1 This pin use together with PS0 to determine the interface protocol between the driver and MCU according to the following table.
PS0 L L H H PS1 L H L H Interface 3-wire SPI (write only) 4-wire SPI (write only) 8080 parallel interface (read and write allowed) 6800 parallel interface (read and write allowed)
REF This pin is an input pin to enable the internal reference voltage used for the internal regulator. When it is high, an internal reference voltage source will be used. When it is low, an external reference voltage source must be provided in VEXT pin if internal regulator is used. VDD Power supply pin. VSS Ground. VCI Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the multiple factor (2X, 3X, 4X, 5X or 6X) times VCI with respect to VS S. Note: 1.) voltage at this input pin must be larger than or equal to VDD . 2.) 6X is avaliable for SSD1821 only. VCC This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries. C1 P, C2 P, C3 P, C 4P, C 5P , C1N and C2N When internal DC-DC voltage converter is used, external capacitor(s) is/are connected among these pins. VL6 This pin is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator. VR This pin is an input of the internal voltage regulator. When the internal resistors network for the voltage regulator is disabled (INTRS is pulled low), external resistors should be connected between VSS and VR, and VR and VL6 , respectively (see application circuit). VEXT This pin is an input to provide an external voltage reference for the internal voltage regulator when REF pin is pulled low.
CS This pin is chip select input. The chip is enabled for display data/ command transfer only when CS is low. D/C This input pin is to identify display data/command cycle. When the pin is high, the data written to the driver will be written into display RAM. When the pin is low, the data will be interpret as command. This pin must be connected to VSS when 3-lines SPI interface is used. R/W(WR) This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, the signal indicates read mode when high and write mode when low. When interfacing to an 8080microprocessor, a data write operation is initiated when R/W(WR) is low and the chip is selected. E(RD) This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, a data operation is initiated when E(RD) is high and the chip is selected. When interfacing to an 8080-microprocessor, a data read operation is initiated when E(RD) is low and the chip is selected. D0-D7 These pins are 8-bit bi-directional data bus to be connected to the microprocessor's data bus. When serial mode is selected, D 7 is the serial data input SDA and D 6 is the serial clock input SCK. INTRS This pin is an input pin to enable the internal resistors network for the voltage regulator when INTRS is high. When it is low, the external resistors R1/R 2 should be connected to VL6, VR and V S S.
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VL5, VL4 , V L3 and VL2 LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship: VL6 > VL5 > VL 4 > VL3 > VL2 > VS S
1:a bias V L5 V L4 V L3 V L2 (a-1)/a*VL6 (a-2)/a*VL6 2/a*V L6 1/a*V L6
For SSD1820A, a equals to 9 at POR. For SSD1821, a equal to 10 at POR. COM0 - COM63/COM79 These pins provide the row driving signal COM0 - COM63/ COM79 to the LCD panel. See Table 1 or 2 about the COM signal mapping in different multiplex ratio N. ICONS This pin is the special icons line COM signal output. SEG0 - SEG127 These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode and standby mode. CL This pin is the external clock input for the device which is enabled by using an extended command. Under normal operation, this pin should be left opened and internal oscillator will be used after power on reset. N/C These No Connection pins should NOT be connected to any signal pins nor shorted together. They should be left open.
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OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module
Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C is high, data is written to Graphic Display Data RAM (GDDRAM). If D/C is low, the input at D0 -D 7 is interpreted as a Command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information. MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D 0 -D7 ), R/ W(WR), D/C, E(RD) and CS. R/W(WR) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The E(RD) and CS input serves as data latch signal (clock) when they are high and low respectively. Refer to Figure 1 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4 below. MPU Parallel 8080-series interface The parallel interface consists of 8 bi-directional data pins (D 0 -D7 ), R/ W(WR), E(RD), D/C and CS. The CS input serves as data latch signal (clock) when it is low. Whether it is display data or status register read is controlled by D/C. R/W(W R) and E(RD) input indicates a write or read cycle when CS is low. Refer to Figure 2 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. MPU Serial 4-wire Interface The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . SDA is shifted into a 8-bit shift register on every rising edge of SCL in the order of D 7 , D 6 ,... D 0 . D/C is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission. MPU Serial 3-wire Interface Operation is similar to 4-wire serial interface while D/ C is not been used. The Display Data Length instruction is used to indicate that a specified number display data byte (1-256) are to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial communication, a hardware reset pulse at RES pin is required to initialize the chip for re-synchronization. Modes of operation 6800 parallel Data Read Data Write Command Read Command Write Yes Yes Status only Yes 8080 parallel Yes Yes Status only Yes Serial No Yes No Yes
R/W(WR)
E(RD)
data bus
N write column address dummy read
n data read1
n+1 data read 2
n+2 data read 3
Figure 4: display data read with the insertion of dummy read
Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 65 = 8320bits for SSD1820A; 128 x 81 = 10368bits for SSD1821. Figure 5, 6 are the description of the GDDRAM address map. For mechanical flexibility, re-mapping on both
Segment and Common outputs are provided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5, 6 show the case in which the display start line register is set at 38H.
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Column address 00H (7FH) Segment Remap Enabled LSB [D0] Page 0 MSB [D7] LSB Page 1 MSB LSB Page 2 MSB LSB Page 3 MSB LSB Page 4 MSB LSB Page 5 MSB LSB Page 6 MSB LSB Page 7 MSB Page 8 (LSB)
Column address 7FH (00H) COM SCAN MODE NORMAL (REMAPPED) COM8 (COM55)
38H
COM63 (COM0) COM0 (COM 63)
COM7 (COM56) ICONS
SEG 0
SEG127
Note:
The configuration in parentheses represent the remapping of Rows and Columns
Figure 5. SSD1820A Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 38H)
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Column address 00H (7FH) Segment Remap Enabled LSB [D0] Page 0 MSB [D7] LSB Page 1 MSB LSB Page 2 MSB LSB Page 3 MSB LSB Page 4 MSB LSB Page 5 MSB LSB Page 6 MSB LSB Page 7 MSB LSB Page 8 MSB LSB Page 9 MSB Page 10 (LSB) SEG 0
Column address 7FH (00H) COM SCAN MODE NORMAL (REMAPPED) COM24 (COM55)
38H
COM79 (COM0) COM0 (COM 79)
COM23 (COM56) ICONS
SEG127
Note:
The configuration in parentheses represent the remapping of Rows and Columns
Figure 6. SSD1821 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 38H)
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Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 7). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable enable Oscillation Circuit enable Buffer (CL)
OSC1 Internal pwell resistor
OSC2
Figure 7. Oscillator Circuitry
LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generate necessary bias voltages. It consists of: 1. 2X, 3X, 4X, 5X and 6X DC-DC voltage converter Please refer to application notes. Please note that SSD1820A works up to 5X and SSD1820AT works up to 4X only. 2. Voltage Regulator Feedback gain control for initial LCD voltage. External resistors are connected between VSS and VR, and between VR and VL6. These resistors are chosen to give the desired VL6 according to the following equation: ed to add to the application circuit as follows:
SSD1820A/21 Series
V SS V L2 V L3 V L4 V L5 V L6
RL RL
RL
RL
+
+
+
+
VL 6
R2 = (1 + ) x V con x G R1 63 - ) x V ref 210
C2
V SS
C2
C2
C2
+ C2
Remarks: 1. C2 = 0.47 ~ 2.0uF 2. RL = 100K ~ 1M Connections for heavy loading applications 4. Contrast Control Software control of 64 voltage levels of LCD voltage. 5. Bias Ratio Selection circuitry Software control of 1/ 4 to 1/10 bias ratio to match the characteristic of LCD panel. Note: SSD1820A has 1/4 to 1/9 bias only. 6. Self adjust temperature compensation circuitry Provide 2 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.05% /o C for SSD1820A and -0.07%/o C for SSD1821 . 193/209 Bit Latch A register carries the display signal information. In 128 X 65/81 displamode. Data will be fed to the HV-buffer Cell and level-shifted to the required level. Level Selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
V con = (1 -
where Vref is the internally generated reference voltage with a known R 1 and R 2. Typical value for V ref is 2.1V R 1 is the resistance of the resistor between V SS and V R . R 2 is the resistance of the resistors between V R and V L6. is the software contrast level from 0 to 63. G = 1 if INTRS = VDD; REF = VDD G = 0.84 if INTRS = VSS; REF = VDD 3. Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (V L6) to give the LCD driving levels (VL2 - VL5 ). A low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. Stablizing Capacitors (0.47~2uF) are required to be connected between these voltage level pins (V L2 - V L5 ) and VSS. If the LCD panel loading is heavy, capacitors and four additional resistors are suggest-
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HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal. Reset Circuit When RES input is low, the chip is initialized to the following: 1. Page address is set to 0 2. Column address is set to 0 3. Display is OFF 4. Display Start Line is set to 0 (GDDRAM page 0, D0) 5. Display Offset is set to 0 (COM0 is mapped to ROW0) 6. 128x64 for SSD1820A / 128x80 for SSD1821 7. Normal/Reverse Display is Normal 8. n-line Inversion Register is 0 9. Entire Display is OFF 10. Power Control Register (VC, VR, VF) is set to (0,0,0) 11. 2X/3X Booster is selected 12. Internal Resistor Ratio register is set to 0H 13. Software Contrast is set to 32 14. LCD Bias Ratio is set to 1/9 for SSD1820A and 1/10 for SSD1821. 15. Normal scan direction of COM outputs 16. Segment remap is disabled (SEG0 display column address 0) 17. Internal oscillator is OFF 18. Test mode is OFF 19. Temperature coefficient is set to PTC0 for SSD1820A and PTC1 for SSD1821. 20. Icon display line is OFF 21. Interface Lock / Unlock register will be clear When RESET command is issued, the following parameters are initialized only: 1. Page address is set to 0 2. Column address is set to 0 3. Initial Display Line is set to 0 (point to display RAM page 0, D0) 4. Internal Resistor Ratio register is set to 0H
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LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 8a and 7b illustrate the desired multiplex scheme with N-line Inversion feature is disabled (default).
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4
Figure 8a. LCD Display Example "0"
TIME SLOT
123456789 ... * N1 234 56 78 9 ... * N12 34 56 78 9 ... * N1 2 3 4 5 6 7 8 9 ... * N
V L6 V L5 COM0 V L4 V L3 V L2 V SS
V L6 V L5 COM1 V L4 V L3 V L2 V SS
V L6 V L5 SEG0 V L4 V L3 V L2 V SS
V L6 V L5 SEG1 V L4 V L3 V L2 V SS
M
* Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 64/80 on POR.
Figure 8b. LCD Driving Signal from SSD1820A/SSD1821
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COMMAND TABLE
Hex 00~0F 10~17 18~1F 20~27 0 0 1 0 0 R2 R1 D7 0 0 D6 D5 0 0 0 0 D4 D3 0 1 C3 0 D2 D1 C2 C1 C6 C5 D0 Command C0 Set Lower Column Address C4 Set Upper Column Address Reserved Comment Sets the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. Sets the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. Reserved
R0 Set Internal Regulator Resis- The internal regulator gain (1+R2/R1)Vcon increases as tor Ratio R2R1R0 is increased from 000b to 111b. The resistor ratio (1+R2/R1) is given by: R2R1R0 = 000: 2.3 (POR) R2R1R0 = 001: 3.0 R2R1R0 = 010: 3.7 R2R1R0 = 011: 4.4 R2R1R0 = 100: 5.1 R2R1R0 = 101: 5.8 R2R1R0 = 110: 6.5 R2R1R0 = 111: 7.2
28~2F
0
0
1
0
1
VC VR V F Set Power Control Register
VC=0: turns OFF the internal voltage booster (POR) VC=1: turns ON the internal voltage booster VR=0: turns OFF the internal regulator (POR) VR=1: turns ON the internal regulator VF=0: turns OFF the output op-amp buffer (POR) VF=1: turns ON the output op-amp buffer
30~3F 40~43 0 x 1 L6 0 L5 0 L4 0 L3 0 L2 x L1 x L0
Reserved Set Display Start Line
Reserved The next command specifies the row address pointer (0-63) of the RAM data to be displayed in COM0. This command has no effect on COMS. The pointer is set to 0 after reset. The next command specifies the mapping of first display line (COM0) to one of ROW0~63. This command has no effect on COMS. COM0 is mapped to ROW0 after reset. The next command specifies the number of lines, excluding COMS, to be displayed. With Icon is disabled (POR), duties 1/16~1/64 or 1/80 could be selected. With Icon enabled, the available duty ratios are 1/17~ 1/65 or 1/81. The next command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. Register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. Value 00000b disables the N-line inversion, which is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should NOT be a multiple of the lines of inversion (n).
44~47
0 x
1
0
0
0
1
x
x C0 x D0
Set Display Offset
C6 C5 1 0
C4 C3 0 1
C2 C1 0 x
48~4B
0 x
Set Multiplex Ratio
D6 D5
D4 D3
D2 D1
4C~4F
0 x
1 x
0 x
0
1
1
x
x N0
Set N-line Inversion
N4 N3
N2 N1
50~57
0
1
0
1
0
B2
B1
B 0 Set LCD Bias
Sets the LCD bias from 1/4 ~ 1/10 according to B2B1B0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7bias 100: 1/8 bias 101: 1/9 bias (POR for SSD1820A) 110: 1/9 bias (for SSD1820A) 1/10 bias (POR for SSD1821) 111: 1/9 bias (for SSD1820A); 1/10 bias (for SSD1821)
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58~63 64~67 0 1 1 0 0 1 B1 B0
Reserved Set DC-DC Conveter Factor
Reserved Sets the DC-DC multiplying factor from 2X to 6X B1B0: 00: 2X/3X (POR, 2X or 3X multiplying depended on the DC-DC conveter configuration) 01: 4X 10: 5X (for SSD1820A) 11: 5X (for SSD1820A); 6X (for SSD1821)
68~80 81 1 x 82~9F A0~A1 1 0 1 0 0 0 0 S0 0 x 0 0 0 0 0 1
Reserved
Reserved
C5 C4
C3 C2
C1 C0
Set Contrast Control Regis- The next command sets one of the 64 contrast levels. ter The darkness increase as the contrast level increase. The level is set to 32 after POR. Reserved Set Segment Re-map Reserved S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 7FH is mapped to SEG0
A2~A3 A4~A5
1 1
0 0
1 1
0 0
0 0
0 1
1 0
C0 E0
Set Icon Enable Set Entire Display On/Off
C0=0: Disable icon row (Mux = 16 to 64/80, POR) C0=1: Enable icon row (Mux = 17 to 65/81) E0=0: Normal display (dispaly according to RAM contents, POR) E0=1: All pixels are ON regardless of the RAM contents *Note: This command will override the effect of "Set Normal/Reverse Display"
A6~A7
1
0
1
0
0
1
1
R0
Set Normal/Reverse Display
R0=0: Normal display (dispaly according to RAM contents, POR) R0=1: Reverse display (ON and OFF pixels are inverted) *Note: This command will not affect the display of the icon lines
A8 A9 AA AB 1 0 1 0 1 0 1 1 1 0 1 0 1 0 0 1
Reserved Set Power Save Mode Reserved Start Internal Oscillator
Reserved Enter Sleep mode Reserved Oscillator is OFF after reset, until this command is issued. This command is required even if external oscillator is used. D0=0: Display OFF (POR) D0=1: Display ON Set GDDRAM page address (0~10) using P3P2P1P0 for RAM access. The page address is sets to 0 after reset. Scan S0=0: Normal mode (POR) S0=1: Remapped mode. COM0 to COM[N-1] becomes COM[N-1] to COM0 when the duty is set to N. See Figure 5/6 as an example for N equals to 64/80. *Note: This command will not affect the display of the icon lines
AE~AF B0~BF
1 1
0 0
1 1
0 1
1 P3
1 P2
1 P1
D0 P0
Set Display On/Off Set Page Address
C0~CF
1
1
0
0
S0
x
x
x
Set COM Direction
Output
D0~E0 E1 1 1 1 0 0 0 0 1
Reserved Exit Power-save Mode
Reserved DC-DC converter, regulator and divider status before entering the power-save mode is restored. At POR, Power-save Mode is released. Initialize some internal registers Reserved The frame will be inverted once per frame Reserved
E2 E3 E4 E5~E7
1
1
1
0
0
0
1
0
Software Reset Reserved
1
1
1
0
0
1
0
0
Exit N-line Inversion Reserved
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E8
1
1
1
0
1
0
0
0
Set Display Data Length
This command is valid only at 3-wire SPI (PS0=PS1=L) The next command specifies the number of bytes of display data to be written after this composite command. D(7:0)=00: 1 byte of display data is to be sent D(7:0)=FF: 256 bytes of display data is to be sent
D7 D6
D5 D4
D3 D2
D1 D0
E9~EF F0~FF 1 1 1 1 x x x x
Reserved Extended Features
Reserved Test mode commands and Extended features, see Extended Command Table.
EXTENDED COMMAND TABLE
Bit Pattern 11110001 00001X2 X 1 X 0 11110010 0010X3 X 2 X 1 X 0 X 3: Select Oscillator Source X 2X 1X 0 : Set Oscillator Value Command X 2X 1X 0 : Set TC Value Comment X 2X 1X 0 = 000: -0.05%/C (POR for 1820A) X 2X 1X 0 = 001: -0.07%/C (POR for 1821) X 3 = 0: Internal RC oscillator is selected (POR) X 3 = 1: External oscillator from CL pin is selected if X3 = 0, X 2 X 1 X 0 = 000: -16% X 2 X 1 X 0 = 001: -10% X 2 X 1 X 0 = 010: 0% (POR) X 2 X 1 X 0 = 011: +10% X 2 X 1 X 0 = 100: +16% X 2 X 1 X 0 = 101: +30% X 2 X 1 X 0 = 110: +54% X 2 X 1 X 0 = 111: +81% 11111101 00010L10 Other than above Reserved L : Interface Lock / Unlock L = 0 Interface Unlock (POR) L = 1 Interface Lock
Read Status Byte
A 8 bits status byte will be placed to the data bus if a read operation is performed if D/C is low. The status byte is defined as follow. D7 BUSY D6 ON D5 RES D4 0 D3 1 D2 0 D1 0 D0 DS0 Comment BUSY=0: Chip is idle BUSY=1: Chip is executing instruction ON=0: Display is OFF ON=1: Dispaly is ON RES=0: Chip is idlex RES=1: Chip is executing reset DS0=0: SSD1820A; DS0=1:SSD1821
Data Read / Write
To read data from the GDDRAM, input High to R/W(WR) pin and D/C pin for 6800-series parallel mode, Low to E(RD) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data is read. See Figure 4 in Func-
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tional Description. To write data to the GDDRAM, input Low to R/W(W R) pin and High to D/ C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. The address will be reset to 0 in next data read/write operation is executed when it is 127.
Address Increment Table (Automatic)
D/C 0 0 1 1 R/W(WR) 0 1 0 1 Comment Write Command Read Status Write Data Read Data Address Increment No No Yes Yes
Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is 127.
Commands Required for R/W(WR) Actions on RAM
R/W(WR) Actions on RAMs Read/Write Data from/to GDDRAM. Commands Required Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data (1011X3 X 2 X 1 X 0 )* (0001X3 X 2 X 1 X 0 )* (0000X3 X 2 X 1 X 0 )* (X 7 X 6X 5 X 4 X 3 X 2 X 1 X 0)
* No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not.
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Command Description Set Display On/Off This command turns the display on/off, by the value of the LSB. Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63/79. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63/79 are assigned to Page 0 to 7/9. Set Page Address This command positions the page address to 0 to 8/10 possible positions in GDDRAM. Refer to figure 5/6. Set Higher Column Address This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127). Set Lower Column Address This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127). Set Segment Re-map This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to figure 5/6. Set Normal/Reverse Display This command sets the display to be either normal/reverse. In normal display, a RAM data of 1 indicates an "ON" pixel while in reverse display, a RAM data of 0 indicates an "ON" pixel. The icon line is not affected by this command.
16.0 14.0 12.0 VL6 Voltage (V) 10.0 011 8.0 6.0 4.0 2.0 0.0 0 7 15 23 31 39 Contrast Control Setting Default TC 47 55 63 010 001 000
Set Entire Display On/Off This command forces the entire display, including the icon row, to be "ON" regardless of the contents of the display data RAM. This command has priority over normal/reverse display. To executed this command, Set Display On command must be sent in advance. Set LCD Bias This command selects a suitable bias ratio (1/4 to 1/9 or 1/10) required for driving the particular LCD panel in use. The POR default for SSD1820A is set to 1/9 bias; and 1/10 bias for SSD1821. Software Reset This command causes some of the internal status of the chip to be initialized: 1. Page address is set to 0 2. Column address is set to 0 3. Initial Display Line is set to 0 (point to display RAM page 0, D0) 4. Internal Resistor Ratio register is set to (0,0,0) 5. Software Contrast is set to 32 Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. Set Power Control Register This command turns on/off the various power circuits associated with the chip. Set Internal Regulator Resistors Ratio This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network (INTRS pin pulled high). When external resistors are used, INTRS must be connected to VSS. The Contrast Control Voltage Range curves is given in the figure below:
IRS Setting 111 110 101 100
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Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing VL6 of the LCD drive voltage provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) contrast control register. It is a compound commands:
Set Contrast Control Register Contrast Level Data
This command enable/disable the Icon display. Start InternalOscillator After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip. Set Display Data Length This two-byte command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte (1256) are to be transmitted. Next byte after the display data string is handled as a command. Set Test Mode This command force the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. Status register Read This command is issued by setting D/C Low during a data read (refer to figure 1 and 2 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. EXTENDED COMMANDS These commands are used, in addition to basic commands, to enable the enhanced features designed in the chips. Set Temperature Coefficient (TC) Value This command is to set 1 out of 2 different temperature coefficients in order to match various liquid crystal temperature grades. Enable external oscillator input. This command enables the external clock input from CL pin. Select Oscillator Source This command is used to adjust the oscillator frequency to desire frame frequency. Set Interface Lock / Unlock After the interface lock command is issued, no more data or commands will be accepted until an interface unlock command is issued.
No
Changes Complete? Yes
Set Display Offset The next command specifies the mapping of display start line (COM0 if display start line register equals to 0) to one of ROW063/79. This command has no effect on COMS. COM0 is mapped to ROW0 after reset. Set Multiplex Ratio This command switches default 64 multiplex mode to any multiplex from 16 to 64/80, if Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 65/81. The chip pads ROW0-ROW63/ROW79 will be switched to corresponding COM signal output as specified in Table 1 or 2. Set Power Save Mode To force the chip to enter Sleep Mode. Exit Power Save Mode This command releases the chip from Sleep Mode and return to normal operation. Set N-line Inversion Number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line inversion operations could be selected. At POR, this operation is disabled. It should be noted that the total number of mux (including the icon line) should NOT be a multiple of the inversion number (n). Or else, some lines will not change their polarity during frame change. Exit N-line Inverstion This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command. Set DC-DC Converter Factor Internal DC-DC converter factor is set by this command. For SSD1820A, 2X to 5X multiplying factors could be selected. For SSD1821, 2X to 6X mutiplying factors could be selected. 2X/3X, 4X, 5X and 6X factors are selected uising this command. Hardware configuration is used for 2X or 3X setup.
Set Icon Enable
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SSD1820A/21 23
MAXIMUM RATINGS* (Voltages Referenced to VSS )
Symbol V DD V CC V CI V in I TA Tstg Booster Supply Voltage Input Voltage Current Drain Per Pin Excluding V DD and V SS Operating Temperature Storage Temperature Range Supply Voltage Parameter Value -0.3 to +4.0 V SS -0.3 to VSS +15.0 V DD to +4.0 V SS -0.3 to VDD +0.3 25 -40 to +85 -65 to +150 Unit V V V V mA C C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V a n d Vout be constrained to the in range VSS < or = (V in or Vout) < or = VDD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either VSS o r VDD ). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS , VDD =1.8 to 3.3V, TA =-40 to 85C; unless otherwise specified.)
Symbol V DD IAC Parameter Logic Circuit Supply Voltage Range Voltage Generator Circuit Supply Voltage Range Access Mode Supply Current Drain (V D D Pins Test Condition (Absolute value referenced to VSS ) V DD = 2.7V, Voltage Generator On, 4X Converter Enabled, Write accessing, Tcyc =3.3MHz, Osc. Freq.=31kHz, Display On. Min 1.8 Typ (at 25C) 2.7 300 Max 3.3 600 Unit V A
IDP1
Display Mode Supply Current Drain (VDD Pins)
V DD = 2.7V, VCC = 10.8V, Voltage Generator Off, external Divider Enabled. Read/Write Halt, Osc. Freq. = 31kHz, Display On, VL6 = 9.0V. V DD = VCI = 2.7V, VCC = 10.8V, Voltage Generator On, 4x DC-DC Converter Enabled, V pin conCI nected to VDD. Internal Divider Enabled. Read/Write Halt, Osc. Freq. = 31kHz, Display On, VL6 = 9.0V. V D D=2.7V, LCD Driving Waveform Off, Osc. Freq. = 31kHz, Read/Write halt. V D D = 2.7V, LCD Driving Waveform Off, Oscillator Off, Read/Write halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Osc. Freq.=31kHz, Regulator Enabled, Divider Enabled. ICC < 20uA Voltage Generator Disabled. Internal Reference Voltage Source Disable (REF pin pulled Low), External Reference voltage input to V E X T pin. Internal Reference Voltage Source Enabled (REF pin pulled High), VE X T pin NC.
-
15
26
A
IDP2
Display Mode Supply Current Drain (VDD Pins)
-
90
120
A
ISB
Standby Mode Supply Current Drain (V DD Pins)
-
8.0
37
A
ISLEEP V CC
Sleep Mode Supply Current Drain (V DD Pins) LCD Driving Voltage Generator Output (V C C Pin)
-
0.5
3
A V
V DD
-
15.0
DC-DC Converter Efficiency V LCD LCD Driving Voltage Input (VCC Pin) V REF External Reference Voltage Input
95 4.0 2.04
99 2.10 15.0 2.16
% V V
Internal Reference Voltage
2.10
V
SSD1820A/21 REV 1.4 01/03 24
SOLOMON
V OH1 V OL1
VL6
Output High Voltage (D 0 -D 7 ) Output Low Voltage (D0-D 7) LCD Driving Voltage Source (VL6 Pin)
Iout = +500A Iout = -500A
0.8*V D
D
-
VD D 0.2*V D
D
V V V
0 Regulator Enabled (VL6 voltage depends on Int/Ext Contrast Control) Regulator Disable V DD Floating
V CC0.5 V -
VL6
LCD Driving Voltage Source (VL6 Pin)
V IH1
Input high voltage (RES, PS0, PS1, CS, D/C, R/W, D0 -D7 , REF, INTRS)
0.8*V D
D
-
VD D
V
V IL1
Input Low voltage (RES, PS0, PS1, CS, D/C, R/W, D 0 -D7 , REF, INTRS) 0 Bias Divider Enabled, 1:a bias ratio V L5 V L4 V L3 V L2 V SS 50
-
0.2*V D
D
V
V L6 V L5 V L4 V L3 V L2 V L6 V L5 V L4 V L3 V L2 IOH
LCD Display Voltage Output (V L6, VL5 , VL4, VL3 , VL2 Pins)\
V L6 (a-1)/a*VL6 (a-2)/a*VL6 2/a*V L6 1/a*V L6 -
VC C V L6 V L5 V L4 V L3 -
V V V V V V V V V V A
LCD Display Voltage Inpu (V L6, VL5 , VL4, VL3 , VL2 Pins)
Voltage reference to V SS , External Voltage Generator, Bias Divider Disabled
Output High Current Source (D 0 -D 7 ) Output Low Current Drain (D 0 -D 7 ) Output Tri-state Current Drain Source (D 0 -D 7 ) Input Current (RES , PS0, PS1, CS , E, D/C, R/W, D0 -D 7 , REF, INTRS) Input Capacitance (all logic pins) Variation of VL6 Output (1.8V < V DD < 3.0V) Temperature Coefficient Compensation*
V out =VDD -0.4V
IOL
V out =0.4V
-
-
-50
A
IO Z IIL/I I H
-1 -1
-
1 1
A A
CIN VL6
Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 Voltage Regulator Enabled (POR for SSD1820A) Voltage Regulator Enabled (POR for SSD1821) -
5 2
7.5 -
pF %
PTC0 PTC1
Temperature Coefficient 0 Temperature Coefficient 1
-0.04 -0.06
-0.05 -0.07
-0.06 -0.08
% %
* The formula for the temperature coefficient is: TC(%)= V L6 at 50C - V L6 at 0C X 50C - 0C 1 V L6 at 25C X 100%
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AC ELECTRICAL CHARACTERISTICS (TA=25C, Voltage referenced to VSS , VDD =VCI =2.7V, unless otherwise specified.)
Symbol FOSC FF R M Parameter Test Condition Min 28.4 Typ(at 25C) 33 Max 39 Unit kHz Oscillation Frequency of Display Timing Generator Internal Oscillator Enabled (SSD1820A/21) Frame Frequency (SSD1820A) Frame Frequency (SSD1821) F OSC 6 x 65 Display ON, Set 128 x 64 Graphic Display Mode, Icon Line Enabled. POR Oscillator Settings F OSC 5 x 81 Display ON, Set 128 x 80 Graphic Display Mode, Icon Line Enabled. POR Oscillator Settings 70 81.5 100 Hz
70
84.6
100
Hz
SSD1820A/21 REV 1.4 01/03 26
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TABLE 3a. Parallel Timing Characteristics (T A=-40 to 85C, VDD =2.7V, V S S=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tO H tACC P WCSL Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) PW CSH tR tF Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 66 0 0 10 2 10 95 40 15 30 30 10 10 ns ns ns ns Typ Max 30 80 25 Unit ns ns ns ns ns ns ns ns ns ns ns
R/W
D/C
tAS E tcycle PW CSL CS tF tDSW D 0 -D 7 (Write data to driver) Valid Data tR
tAH
PW CSH
tDHW
tACC D0 -D7 (Read data from driver) Valid Data
tDHR
tO H
Figure 1a. Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
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TABLE 3b. Parallel Timing Characteristics (TA =-40 to 85C, VDD =1.8V, VSS =0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tO H tACC P WCSL Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) PW CSH tR tF Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 80 0 0 15 5 15 120 55 20 40 40 Typ Max 40 100 35 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
R/W
D/C
tAS E tcycle PW CSL CS tF tDSW D 0 -D 7 (Write data to driver) Valid Data tR
tAH
PW CSH
tDHW
tACC D0 -D7 (Read data from driver) Valid Data
tDHR
tO H
Figure 1b. Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
SSD1820A/21 REV 1.4 01/03 28
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TABLE 4a. Parallel Timing Characteristics (TA=-40 to 85C, V DD =2.7V, VSS =0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) PW CSH tR tF Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 66 0 0 10 2 10 95 40 15 30 30 10 10 ns ns ns ns Typ Max 30 80 25 Unit ns ns ns ns ns ns ns ns ns ns ns
D/C
tAS
tAH
WR (R/W)
RD (E) tcycle PW CSL CS tF tDSW D 0 -D 7 (Write data to driver) Valid Data tR tDHW PW CSH
tACC D0 -D7 (Read data from driver) Valid Data
tDHR
tO H
Figure 2a. Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
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TABLE 4b. Parallel Timing Characteristics (T A=-40 to 85C, VDD =1.8V, V S S=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) PW CSH tR tF Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 80 0 0 15 5 15 120 55 20 40 40 Typ Max 40 100 35 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D/C
tAS
tAH
WR (R/W)
RD (E) tcycle PW CSL CS tF tDSW D0 -D 7 (Write data to driver) Valid Data tR tDHW PW CSH
tACC D 0 -D7 (Read data from driver) Valid Data
tDHR
tO H
Figure 2b. Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
SSD1820A/21 REV 1.4 01/03 30
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TABLE 5a. Serial Timing Characteristics (TA=-40 to 85C, VDD =2.7V, VSS =0V)
Symbol tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Parameter Min 59 10 5 10 5 10 10 10 20 Typ Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
D/C (Required if PS1 = H) tAS CS tCSS tcycle tCLKL SCK tF tDSW SDA Valid Data tR tDHW tCLKH tAH tCSH
CS
SCK
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3a. Serial Timing Characteristics (PS0 = L)
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TABLE 5b. Serial Timing Characteristics (T A=-40 to 85C, VDD =1.8V, V S S=0V)
Symbol tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Parameter Min 70 15 10 15 10 15 15 15 30 Typ Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
D/C (Required if PS1 = H) tAS CS tCSS tcycle tCLKL SCK tF tDSW SDA Valid Data tR tDHW tCLKH tAH tCSH
CS
SCK
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3b. Serial Timing Characteristics (PS0 = L)
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Application Circuit: Bias divider enabled with external VCC .
ICONS COM0 : COM6 COM7 : COM32 COM33 : COM39
DISPLAY PANEL SIZE 128 x 80 + 2 ICON LINES
COM40 : COM47 COM48 : COM73 COM74 : COM79 ICONS
Remapped COM SCAN Direction [Command: C8]
SEG0 -------------------------------- SEG127
Segment Remapped [Command: A1]
S EG1 2 7 S EG1 2 6 : : : : : : : : : : : : SE G6 4 SE G6 3 : : : : : : : : : : : : : : : : : : SE G2 SE G1 SE G0 CO M4 6 CO M4 5 CO M4 4 CO M4 3 CO M4 2 CO M4 1 CO M4 0
Remapped COM SCAN Direction [Command: C8]
Remapped COM SCAN Direction [Command: C8]
COM 7 3 : : COM 7 9 IC ON S
VL2 VL3 VL4 VL5 VL6
Remapped COM SCAN Direction [Command: C8]
VR
Remapped COM SCAN Direction [Command: C8]
R2 REF VCC VSS D/C E D0 - D7 INTRS R/W RES CS
R1 VSS Five captacitors and four optional resistors for large loading panel. See description on P.15 Optional for External Resistors Gain Control [INTRS pulled to VSS]
See Application Notes on P.35
VDD=2.7V External Vcc=10.8V
SOLOMON
COM 3 9 : : COM 3 3 COM 3 2
NC COM47 COM48 : : : COM52 COM53 : : : COM71 COM72 NC
IC ON S C OM 0 C OM 1 C OM 2 C OM 3 C OM 4 C OM 5
SSD1821 DIE
80 MUX (DIE FACE UP)
NC COM6 COM7 : : : COM20 COM19 : : : COM30 COM31 NC
Remapped COM SCAN Direction [Command: C8]
0.47F - 2.0F
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SSD1820A/21 33
Application Circuit: 4X Booster, Bias divider disabled.
ICONS COM0 : COM6 COM7 : COM32 COM33 : COM39
DISPLAY PANEL SIZE 128 x 80 + 2 ICON LINES
COM40 : COM47 COM48 : COM73 COM74 : COM79 ICONS
Remapped COM SCAN Direction [Command: C8]
SEG0 -------------------------------- SEG127
Segment Remapped [Command: A1]
S EG1 2 7 S EG1 2 6 : : : : : : : : : : : : SE G6 4 SE G6 3 : : : : : : : : : : : : : : : : : : SE G2 SE G1 SE G0 CO M4 6 CO M4 5 CO M4 4 CO M4 3 CO M4 2 CO M4 1 CO M4 0
Remapped COM SCAN Direction [Command: C8]
Remapped COM SCAN Direction [Command: C8]
COM 7 3 : : COM 7 9 IC ON S
VSS VCC C3P C1NC1P C2P C2N
VDD
VCI
Remapped COM SCAN Direction [Command: C8]
VL2 VL3 VL4 VL5 VL6
VR
Remapped COM SCAN Direction [Command: C8]
D0 - D7 and Control Bus
R2
1F 1 F 1F 1F
VSS VCI/VDD=2.7V
R1 Optional for External Resistors Gain Control [INTRS pulled to VSS]
See Application Notes on P.35
RES
VSS
COM 3 9 : : COM 3 3 COM 3 2
NC COM47 COM48 : : : COM52 COM53 : : : COM71 COM72 NC
IC ON S C OM 0 C OM 1 C OM 2 C OM 3 C OM 4 C OM 5
SSD1821 DIE
80 MUX (DIE FACE UP)
NC COM6 COM7 : : : COM20 COM19 : : : COM30 COM31 NC
Remapped COM SCAN Direction [Command: C8]
SSD1820A/21 REV 1.4 01/03 34
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Application Circuit: DC-DC Converter Circuit Configuration
SSD1820A and SSD1821 IC work from 2X to 5X and 2X to 6X DC-DC converter respectively. For the capactior connections, please refer to below circuit diagrams. Note that if the capacitor connection does not match with the software setting of DC-DC Converter Factor (0x64~0x67), abnormal current consumption will be observed.
2x Converter
V SS V CC C 5P C 3P C 1N C 1P C 2P C 2N C 4P + +
3x Converter
V SS V CC C 5P C 3P C 1N C 1P C 2P C 2N C 4P + +
4x Converter
V SS V CC C 5P C 3P C 1N C 1P C 2P C 2N C 4P + +
+
+
+
5x Converter
V SS V CC C 5P C 3P C 1N C 1P C 2P C 2N C 4P + + + +
6x Converter
V SS V CC C 5P + C 3P C 1N C 1P C 2P C 2N C 4P + + + +
+
+
*Note: Capacitor value = 1.0uF to 4.7uF
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SSD1820A/21 35
APPLICATION NOTE 1: ESD PROTECTION CIRCUIT
For SSD1820A/21 IC, it is recommended to design a simple protection circuit to prevent from unexpected external interference. This is useful especially the designed product has to go through unexpected electrostatic discharge. Figure 1 is an example of the common circuit used.
(Port output pin)
R RES
Microproesscor unit
C
Typical value: C = 1000nF; R = 3 ~ 10K ohm;
Figure 9: Additional ESD protection circuit
Figure 9 shows one of the most common connection design of the LCD driver IC and the main Microprocessor (MCU) unit, the RES pin of the driver is connected directly to one of the port of the MCU. When external charge is brought near the device, or electrostatic charge (a spike), the charge will be induced inside the device and it will discharge by finding its way to the shortest path to ground. This discharge sometimes will affect the normal operation of the device, causing data disruption inside RAM or internal register s, or even re-initialize / reset the device. The IC design is in-built with a protection circuit (or a diode circuit to the power a nd ground rails), to protect the I/O pins from external charge or spike. Since the diode circuit in the IC is very small, the protection of the circuit is limited. Therefore, it is very useful to build an external device to help prevent the disturbance. it is easy to add a capacitor across the RES pin, this will have a big improvement on the stability of the driver IC. In addition, more protection can be done by adding a resistor in series, directly in between the RES pin of the driver IC and the port of the MCU. This will create a filter (R-C circuit) effect, that will be able to eliminate external noises entering the RES pin of the driver IC. The value of the capacitor and resistor used largely depend on the application printed circuit board design. It is recommended to test and evaluate to find out the best capacitor value for a particular design application. However, for mobile communication devices (eg mobile phones), a lot of applications there is a 1nF capacitor placed across the RES pin and ground.
SSD1820A/21
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SSD1820AT TAB PACKAGE DIMENSION (1 OF 3) DO NOT SCALE THIS DRAWING
NOTES 1. GENERAL TOLERANCE: 0.050MM 2. ALL CHAMFER IS R0.20 3. MATERIAL PI: UPILEX-S 75um+6 THICKNESS ADHESIVE: TORAY #7100 12um2 THICKNESS CU: FQ-VLP 18um FLEX COATING: FS-100 SOLDER RESIST: AE-70-M11 2614um 4. PLATING SN: 0.350.05um 5. OPTIONAL FEATURE FOR SSL EXTERNAL USE ONLY WHICH MAY BE REPLACED BY O2.0MM HOLE 6. 4 SPROCKET HOLES (19.00mm)FOR 1 TAPE
SOLOMON
REV 1.4 01/03
SSD1820A/21 37
SSD1820AT TAB PACKAGE DIMENSION (2 OF 3) DO NOT SCALE THIS DRAWING
SSD1820A/21 REV 1.4 01/03 38
SOLOMON
SSD1820AT TAB PACKAGE DIMENSION (3 OF 3) DO NOT SCALE THIS DRAWING
SOLOMON
REV 1.4 01/03
SSD1820A/21 39
SSD1821T TAB PACKAGE DIMENSION (1 OF 3) DO NOT SCALE THIS DRAWING
NOTES 1. GENERAL TOLERANCE: 0.050MM 2. ALL CHAMFER IS R0.20 3. MATERIAL PI: UPILEX-S 75um+6 THICKNESS ADHESIVE: TORAY #7100 12 2um THICKNESS CU: FQ-VLP 25um 5um FLEX COATING: FS-100L SOLDER RESIST: AR-7100 26 14um GENERAL TOLERANCE 0.300mm 4. PLATING SN: 0.35 0.05um (0.2 0.05um PURE TIN) 5. OPTIONAL FEATURE FOR SSL EXTERNAL USE ONLY WHICH MAY BE REPLACED BY O2.0MM HOLE 6. 4 SPROCKET HOLES (19.00mm) FOR 1 TAPE
SSD1820A/21 REV 1.4 01/03 40
SOLOMON
SSD1821T TAB PACKAGE DIMENSION (2 OF 3) DO NOT SCALE THIS DRAWING
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REV 1.4 01/03
SSD1820A/21 41
SSD1821T TAB PACKAGE DIMENSION (3 OF 3) DO NOT SCALE THIS DRAWING
SSD1820A/21 REV 1.4 01/03 42
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Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arisin g out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incident al damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to suppo rt or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fe es arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
SSD1820A/21

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